As one method of downsizing and reducing power consumption of a liquid crystal display device, there is known a method of integrally forming pixel circuits and a drive circuit for the pixel circuits on the same substrate. When using this method, the drive circuit is configured by thin-film transistors (hereinafter referred to as TFTs) made of such as low-temperature polysilicon and CG silicon (Continuous Grain Silicon).
On the other hand, in order to improve the reliability of the liquid crystal display device, it is preferable to reduce the number of signal lines connected to a liquid crystal panel. Therefore, there is also known a method of using a serial interface for a signal input to the liquid crystal panel (see FIG. 15). A liquid crystal display device illustrated in FIG. 15 is provided with a liquid crystal panel 71 in which a pixel circuit 72, a drive circuit 73, and a serial interface circuit 74 are integrally formed on a glass substrate. The serial interface circuit 74 converts differential signals inputted from two input terminals DAT(+) and DAT(−) into non-differential signals, performs serial/parallel conversion, and outputs these signals to the drive circuit 73. The drive circuit 73 drives the pixel circuit 72 based on the signals outputted from the serial interface circuit 74. It should be appreciated that signals inputted through the serial interface are not limited to differential signals, and can be non-differential signals.
For example, using a parallel interface when inputting 6-bit video signals for RGB to the liquid crystal panel requires 18 signal lines for inputting the video signals. In contrast, when using the serial interface, only two (in the case of differential signals) or one (in the case of non-differential signals) signal line(s) are/is required for inputting video signals.
When using the serial interface, an input signal is required to change at a higher speed compared to the case in which the parallel interface is used. However, as a wiring delay (RC delay) occurs in a signal line connected to the liquid crystal panel, it is practically impossible to cause an input signal to the liquid crystal panel to change at a high speed. Consequently, when using the serial interface, it is necessary to reduce a voltage amplitude of the input signal to the liquid crystal panel. For example, a differential signal having amplitude of 200 mVp-p centering a common mode voltage Vcm is commonly used in LVDS (Low-Voltage Differential Signaling) as illustrated in FIG. 16, and it is also necessary to reduce the voltage amplitude of the input signal in this manner when the serial interface is used for the signal input to the liquid crystal panel.
In the following, a case in which a differential signal is used for the signal input to a liquid crystal panel is considered. In this case, in order to convert an inputted differential signal to a non-differential signal, a comparator circuit for comparing two voltages is provided for an input stage of the liquid crystal panel. An operation speed of the comparator circuit is heavily affected by characteristics (in particular, a threshold voltage) of transistors that configure the comparator circuit and a common mode voltage of the input signal.
As a comparator circuit that converts a differential signal to a non-differential signal, there has been known a comparator circuit as illustrated in FIG. 17. A comparator circuit 80 illustrated in FIG. 17 is a circuit based on a differential amplifier circuit, compares two voltages inputted from the two input terminals DAT(+) and DAT(−), and outputs a result of the comparison through an output terminal OUT at a power-supply voltage amplitude. The comparator circuit 80 provides an advantageous effect of operating at a high speed due to a high gain, but has a problem of being susceptible to fluctuation of the common mode voltage of the input signal (the operation speed easily changes as the common mode voltage changes).
Further, Non-Patent Document 1 describes an auto-bias comparator circuit illustrated in FIG. 18. A comparator circuit 90 illustrated in FIG. 18 is configured to include two inverters between two power supply wires, and transistors 95 and 96 which supply a bias voltage common to the two inverters are provided between the two power supply wires.
According to the comparator circuit 90, when a voltage supplied to the input terminal DAT(+) becomes greater than a voltage supplied to the input terminal DAT(−), a current that flows through a transistor 91 increases and a current that flows through a transistor 92 decreases. Consequently, a voltage of a bias node Nb decreases. With this, a current that flows through the transistor 96 increases, and an increase of a voltage of the output terminal OUT is facilitated. Along with this, a current that flows through the transistor 95 decreases, and a decrease of the voltage of the output terminal OUT is suppressed. As a result, the voltage of the output terminal OUT increases.
On the other hand, when the voltage supplied to the input terminal DAT (+) becomes smaller than the voltage supplied to the input terminal DAT (−), the current that flows through the transistor 91 decreases and the current that flows through the transistor 92 increases. Consequently, the voltage of the bias node Nb increases. With this, the current that flows through the transistor 95 increases, and a decrease of the voltage of the output terminal OUT is facilitated. Along with this, the current that flows through the transistor 96 decreases, and an increase of the voltage of the output terminal OUT is suppressed. As a result, the voltage of the output terminal OUT decreases. In this manner, the comparator circuit 90 compares the two input voltages.
Techniques related to the present invention are also described in documents listed below. Patent Document 1 describes an example of a signal level conversion circuit provided for an input stage of a liquid crystal panel. Patent Document 2 describes an example of a TFT having two gate terminals (double gate TFT).    [Patent Document 1] Japanese Laid-Open Patent    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2007-157986    [Non-Patent Document 1] M. Bazes, “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, pp. 165-168, February 1991.